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1996 data sheet item program memory data memory part number (rom) internal high-speed ram internal buffer ram internal expanded ram m pd78052y 16 kbytes 512 bytes 32 bytes no m pd78053y 24 kbytes 1024 bytes m pd78054y 32 kbytes m pd78055y 40 kbytes m PD78056Y 48 kbytes m pd78058y 60 kbytes 1024 bytes description the m pd78052y, 78053y, 78054y, 78055y, 78056y, and 78058y versions add the i 2 c bus control function to the m pd78052, 78053, 78054, 78055, 78056, and 78058, and are suitable for application in av products. various peripheral hardware such as 8-bit resolution d/a converter, timer, serial interface, real-time output port and interrupt functions are incorporated. the 78p058y, a one-time prom or eprom version which can be operated in the same supply voltage as for the mask rom version, and various development tools are also available. detailed function descriptions, etc., are provided in the following user's manual. be sure to read it when designing. m pd78054, 78054y subseries users manual : u11747e 78k/0 series users manual instructions : u12326e features ? internal high-capacity rom and ram ? external memory expansion space : 64 kbytes 8-bit single-chip microcontroller mos integrated circuit 1993 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y ? minimum instruction execution time can be varied from high-speed (0.4 m s) to ultra-low-speed (122 m s) ? i/o ports : 69 (n-ch open-drain : 4) ? 8-bit resolution a/d converter: 8 channels ? 8-bit resolution d/a converter: 2 channels ? serial interface : 3 channels (i 2 c bus mode : 1 channel) ? timer : 5 channels ? supply voltage : v dd = 2.0 to 6.0 v applications cellular phones, pagers, printers, av equipment, airconditioners, cameras, ppc, fuzzy home applicances, vending machines, etc. the mark shows major revised points. document no. u10906ej2v0ds00 (2nd edition) date published september 1997 n printed in japan the information in this document is subject to change without notice.
2 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y ordering information part number package m pd78052ygc-xxx-8bt 80-pin plastic qfp (14 x 14 mm) m pd78053ygc-xxx-8bt 80-pin plastic qfp (14 x 14 mm) m pd78054ygc-xxx-8bt 80-pin plastic qfp (14 x 14 mm) m pd78055ygc-xxx-8bt 80-pin plastic qfp (14 x 14 mm) m PD78056Ygc-xxx-8bt 80-pin plastic qfp (14 x 14 mm) m pd78058ygc-xxx-8bt 80-pin plastic qfp (14 x 14 mm) remark xxx indicates the rom code suffix.
3 m pd78052 y , 78053 y , 78054 y , 78055 y , 78056 y , 78058y 78k/0 series development the following shows the 78k/0 series products development. subseries names are shown inside frames. not e under planning 100-pin 100-pin 100-pin 64-pin 64-pin 64-pin 64-pin 80-pin 80-pin 100-pin fip driver lcd driver 80-pin iebus supported under mass production under development y subseries provide i 2 c bus interface function 78k/0 series low voltage (1.8 v) operation version of the pd78014, enhanced rom and ram variation added an a/d and 16-bit timer/event to the pd78002 basic subseries for controller on-chip uart, operatable at a low-voltage (1.8 v) enhanced i/o ports, fip controller/driver of the pd78044f, total display outputs: 53 added an n-ch open-drain input/output to the pd78044f, 100-pin enhanced i/o ports, fip controller/driver of the pd78044h, total display outputs: 48 total display outputs: 34 64-pin 64-pin inverter controller enhanced a/d of the pd780924 on-chip inverter control circuit and uart, emi noise reduced version 80-pin basic subseries for fip drive, total display outputs: 34 basic subseries for lcd driving, on-chip uart emi noise reduced version of the pd78098 added an iebus controller to the pd78054 42/44-pin added a/d to the pd78002 64-pin 64-pin 64-pin enhanced a/d of the pd780024 enhanced serial i/o of the pd78018f, emi noise reduced version emi noise reduced version of the pd78018f emi noise reduced version of the pd78064 enhanced sio to the pd78064 and expanded rom and ram pd78p091 4 64-pin lv incorporated pwm output, lv digital code decorder, and hsync counter 80-pin emi noise reduced version of the pd78078 added uart, and d/a to the pd78014 and enhanced i/o ports 80-pin 100-pin rom-less versions of the pd78078 emi noise reduced version of the pd78054 100-pin 80-pin enhanced serial i/o of the pd78078y with limited number of functions enhanced serial i/o of the pd78054, emi noise reduced version note 100-pin added a timer and enhanced external interface to the pd78054 subseries 100-pin controller m m m m m m m m m m m m m m m m m m m m m m 80-pin meter controller automobile meter drive controller/driver incorporated pd780973 m pd78098b m pd78064 m pd78064b m pd780308 m pd78044f m pd78044h m pd780228 m pd780208 m pd780924 m pd780964 m 64-pin enhanced the inverter control, timer, and sio of the pd78064. expanded rom and ram. m pd780988 m pd78083 m pd78002 m pd780001 m pd78014 m pd78018f m pd78014h m pd780024 m pd780034 m pd78054 m pd78058f m pd780058 m pd78070a m pd78078 m pd78075b m pd78075by m pd78078y m pd78070ay m pd780018ay m pd780058y m pd78058fy m pd78054y m pd780034y m pd780024y m pd78018fy m pd78014y m pd78002y m pd780308y m pd78064y m pd78098 m
4 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y the major functional differences among the subseries are shown below. function rom serial interface i/o v dd min. subseries name capacity value control m pd78075by 32 k to 40 k 3-wire/2-wire/i 2 c : 1 ch 88 1.8 v m pd78078y 48 k to 60 k with automatic transmit/receive function, 3-wire : 1 ch m pd78070ay C 3-wire/uart : 1 ch 61 2.7 v m pd780018ay 48 k to 60 k with automatic transmit/receive function, 3-wire : 1 ch 88 time division 3-wire : 1 ch i 2 c bus (multi master supported) : 1 ch m pd780058y 24 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 68 1.8 v with automatic transmit/receive function, 3-wire : 1 ch 3-wire/time division uart : 1 ch m pd78058fy 48 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 69 2.7 v with automatic transmit/receive function, 3-wire : 1 ch m pd78054y 16 k to 60 k 3-wire/uart : 1 ch 2.0 v m pd780034y 8 k to 32 k uart : 1 ch 51 1.8 v 3-wire : 1 ch m pd780024y i 2 c bus (multi master supported) : 1 ch m pd78018fy 8 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 53 with automatic transmit/receive function, 3-wire : 1 ch m pd78014y 8 k to 32 k 3-wire/2-wire/sbi/i 2 c : 1 ch 2.7 v with automatic transmit/receive function, 3-wire : 1 ch m pd78002y 8 k to 16 k 3-wire/2-wire/sbi/i 2 c : 1 ch lcd m pd780308y 48 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 57 2.0 v driver 3-wire/time division uart : 1 ch 3-wire : 1 ch m pd78064y 16 k to 32 k 3-wire/2-wire/i 2 c : 1 ch 3-wire/uart : 1 ch remark the functions other than the serial interface are the same as those of subseries products without the suffix y.
5 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y overview of function product name item m pd78052y m pd78053y m pd78054y m pd78055y m PD78056Y m pd78058y internal rom 16 kbytes 24 kbytes 32 kbytes 40 kbytes 48 kbytes 60 kbytes memory high-speed ram 512 bytes 1024 bytes buffer ram 32 bytes expanded ram none 1024 bytes memory space 64 kbytes general registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time on-chip minimum instruction execution time cycle modification function when main system clock selected 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0-mhz operation) when subsystem clock selected 122 m s (@ 32.768-khz operation) instruction set ? 16-bit operation ? multiplication/division (8 bits 8 bits,16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. i/o ports total : 69 ? cmos input : 0 2 ? cmos i/o : 63 ? n-ch open-drain i/o : 4 a/d converter ? 8-bit resolution 8 channels d/a converter ? 8-bit resolution 2 channels serial interface ? 3-wire serial i/o/2-wire serial i/o mode/i 2 c bus mode selectable: 1 channel ? 3-wire serial i/o mode (on-chip max. 32-byte automatic data transmit/receive function): 1 channel ? 3-wire serial i/o/uart mode selectable : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer output 3 (14-bit pwm output 1) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@ 5.0-mhz operation with main system clock) 32.768 khz (@ 32.768-khz operation with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@ 5.0-mhz operation with main system clock) vectored maskable internal interrupt : 13, external interrupt : 7 interrupt non-maskable internal interrupt : 1 sources software 1 test input internal : 1, external : 1 supply voltage v dd = 2.0 to 6.0 v operating ambient temperature t a = C40 to +85 c package ? 80-pin plastic qfp (14 14 mm)
6 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y contents 1. pin configuration (top view) .............................................................................................................. 7 2. block diagram ............................................................................................................................... .......... 9 3 pin functions ............................................................................................................................... ........... 10 3.1 port pins ............................................................................................................................... ............... 10 3.2 non-port pins ............................................................................................................................... ........ 12 3.3 pin i/o circuits and recommended connection of unused pins ................................................ 14 4. memory space ............................................................................................................................... ............. 18 5. peripheral hardware function features .................................................................................. 19 5.1 ports ............................................................................................................................... ........................ 19 5.2 clock generator ............................................................................................................................... .... 20 5.3 timer/event counter ............................................................................................................................ 20 5.4 clock output control circuit .............................................................................................................. 23 5.5 buzzer output control circuit ........................................................................................................... 23 5.6 a/d converter ............................................................................................................................... ........ 24 5.7 d/a converter ............................................................................................................................... ........ 25 5.8 serial interfaces ............................................................................................................................... .... 25 5.9 real-time output port functions ...................................................................................................... 27 6. interrupt functions and test functions .................................................................................... 28 6.1 interrupt functions ............................................................................................................................ 28 6.2 test functions ............................................................................................................................... ....... 32 7. external device expansion functions .......................................................................................... 33 8. standby function ............................................................................................................................... ..... 33 9. reset function ............................................................................................................................... ........... 33 10. instruction set ............................................................................................................................... .......... 34 11. electrical specifications ................................................................................................................... 37 12. characteristic curves (reference value) ................................................................................. 64 13. package drawing ............................................................................................................................... ...... 66 14. recommended soldering conditions ............................................................................................. 67 appendix a. development tools ............................................................................................................ 68 appendix b. related documents ........................................................................................................... 70
7 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y cautions 1. ic (internally connected) pin should be connected directly to v ss . 2. av dd pin should be connected to v dd pin. 3. av ss pin should be connected to v ss pin. 1. pin configuration (top view) 80-pin plastic qfp (14 14 mm) m pd78052ygc-xxx-8bt m pd78053ygc-xxx-8bt m pd78054ygc-xxx-8bt m pd78055ygc-xxx-8bt m PD78056Ygc-xxx-8bt m pd78058ygc-xxx-8bt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p40/ad0 p41/ad1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 ic x1 x2 v dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd
8 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y pcl : programmable clock rd : read strobe reset : reset rtp0 to rtp7 : real-time output port r x d : receive data sb0, sb1 : serial bus sck0 to sck2 : serial clock scl : serial clock sda0, sda1 : serial data si0 to si2 : serial input so0 to so2 : serial output stb : strobe ti00, ti01 : timer input ti1, ti2 : timer input to0 to to2 : timer output t x d : transmit data v dd : power supply v ss : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) a8 to a15 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck : asynchronous serial clock astb : address strobe av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock ic : internally connected intp0 to intp6 : interrupt from peripherals p00 to p07 : port0 p10 to p17 : port1 p20 to p27 : port2 p30 to p37 : port3 p40 to p47 : port4 p50 to p57 : port5 p60 to p67 : port6 p70 to p72 : port7 p120 to p127 : port12 p130, p131 : port13
9 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 2. block diagram remark the internal rom and ram capacity depends on the product. port0 port1 port2 port3 port4 port5 port6 port7 port12 port13 real-time output port external access system control 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer serial interface 0 serial interface 1 serial interface 2 a/d converter d/a converter buzzer output interrupt control watch timer 78k/0 cpu core rom ram to0/p30 ti00/intp0/p00 ti01/intp1/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 av dd av ss av ref0 ani0/p10 to ani7/p17 ano0/p130, ano1/p131 av ss av ref1 intp0/p00 to intp6/p06 buz/p36 pcl/p35 clock output control v dd v ss ic p00 p01 to p06 p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p72 p120 to p127 p130, p131 rtp0/p120 to rtp7/p127 ad0/p40- ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2
10 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 3. pin functions 3.1 port pins (1/2) notes 1. when using the p07/xt1 pins as an input port, set 1 in bit 6 (frc) of the processor clock control register (pcc). on-chip feedback resistor of the subsystem clock oscillator should not be used. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input pins, set port 1 to the input mode. the pull-up resistor is disabled automatically. pin name i/o function after alternate reset function p00 input port 0 input only input intp0/ti00 p01 input/ 8-bit i/o port input/output can be specified bit-wise. input intp1/ti01 p02 output when used as an input port, on-chip pull-up resistor intp2 p03 can be used by software. intp3 p04 intp4 p05 intp5 p06 intp6 p07 note 1 input input only input xt1 p10 to p17 input/ port 1 input ani0 to ani7 output 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. note 2 p20 input/ port 2 input si1 p21 output 8-bit input/output port. so1 p22 input/output can be specified bit-wise. sck1 p23 when used as an input port, on-chip pull-up resistor can be used by stb p24 software. busy p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 input/ port 3 input to0 p31 output 8-bit input/output port. to1 p32 input/output can be specified bit-wise. to2 p33 when used as an input port, on-chip pull-up resistor can be used by ti1 p34 software. ti2 p35 pcl p36 buz p37 p40 to p47 input/ port 4 input ad0 to ad7 output 8-bit input/output port. input/output can be specified in 8-bit unit. when used as an input port, on-chip pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection.
11 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 3.1 port pins (2/2) pin name i/o function after alternate reset function p50 to p57 input/ port 5 input a8 to a15 output 8-bit input/output port. led can be driven directly. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. p60 input/ port 6 n-ch open-drain input/output port. input p61 output 8-bit input/outport port. on-chip pull-up resistor can be p62 input/output can be specified specified by mask option. p63 bit-wise. led can be driven directly. p64 when used as an input port, input rd p65 on-chip pull-up resistor can be used wr p66 by software. wait p67 astb p70 input/ input si2/rxd p71 output so2/txd p72 sck2/asck p120 to p127 input/ port 12 input rtp0 to rtp7 output 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. p130, p131 input/ port 13 input ano0, ano1 output 2-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 7 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software.
12 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 input external interrupt request input for which the effective edge (rising input p00/ti00 intp1 edge, falling edge, or both rising edge and falling edge) can be p01/ti01 intp2 specified. p02 intp3 p03 intp4 p04 intp5 p05 intp6 p06 si0 input serial interface serial data input. input p25/sb0/sda0 si1 p20 si2 p70/rxd so0 output serial interface serial data output. input p26/sb1/sda1 so1 p21 so2 p71/txd sb0 input/ serial interface serial data input/output. input p25/si0/sda0 sb1 output p26/so0/sda1 sda0 p25/si0/sb0 sda1 p26/so0/sb1 sck0 input/ serial interface serial clock input/ output input p27/scl sck1 output p22 sck2 p72/asck scl p27/sck0 stb output serial interface automatic transmit/receive strobe output. input p23 busy input serial interface automatic transmit/receive busy input. input p24 rxd input asynchronous serial interface serial data input. input p70/si2 txd output asynchronous serial interface serial data output. input p71/so2 asck input asynchronous serial interface serial clock input. input p72/sck2 ti00 input external count clock input to the 16-bit timer (tm0) input p00/intp0 ti01 capture trigger signal input to the capture register (cr00) p01/intp1 ti1 external count clock input to the 8-bit timer (tm1) p33 ti2 external count clock input to the 8-bit timer (tm2) p34 to0 output 16-bit timer (tm0) output (dual-function as 14-bit pwm output) input p30 to1 8-bit timer (tm1) output p31 to2 8-bit timer (tm2) output p32 pcl output clock output (for main system clock, subsystem clock trimming). input p35 buz output buzzer output. input p36 rtp0 to rtp7 output real-time output port by which data is output in synchronization with a trigger. input p120 to p127 ad0 to ad7 input/ low-order address/data bus at external memory expansion. input p40 to p47 output a8 to a15 output high-order address bus at external memory expansion. input p50 to p57 rd output external memory read operation strobe signal output. input p64 wr external memory write operation strobe signal output. p65
13 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 3.2 non-port pins (2/2) pin name i/o function after dual- reset function pin wait input wait insertion at external memory access. input p66 astb output strobe output which latches the address information output at port 4 input p67 and port 5 to access external memory. ani0 to ani7 input a/d converter analog input. input p10 to p17 ano0, ano1 output d/a converter analog output. input p130, p131 av ref0 input a/d converter reference voltage input. av ref1 input d/a converter reference voltage input. av dd a/d converter analog power supply. connect to v dd av ss ground potential of a/d converter and d/a converter. connect to v ss reset input system reset input. x1 input main system clock oscillation crystal connection. x2 xt1 input subsystem clock oscillation crystal connection. input p07 xt2 v dd positive power supply. v ss ground potential. ic internally connected. connect directly to v ss .
14 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. input/output circuit type of each pin (1/2) pin name input/output i/o recommended connection when used circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a input/output independently connect to v ss through resistor. p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 input/output independently connect to v dd or v ss through resistor. p20/si1 8-a p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0/sda0 10-a p26/so0/sb1/sda1 p27/sck0/scl p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0 to p47/ad7 5-e independently connect to v dd through resistor. p50/a8 to p57/a15 5-a independently connect to v dd or v ss through resistor. p60 to p63 13-b independently connect to v dd through resistor. p64/rd 5-a independently connect to v dd or v ss through resistor. p65/wr p66/wait p67/astb
15 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y table 3-1. input/output circuit type of each pin (2/2) pin name input/output i/o recommended connection when used circuit type p70/si2/rxd 8-a input/output independently connect to v dd or v ss through resistor. p71/so2/txd 5-a p72/sck2/asck 8-a p120/rtp0 to p127/rtp7 5-a p130/ano0 , p131/ano1 12-a independently connect to v ss through resistor. reset 2 input xt2 16 leave open. av ref0 connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . ic connect directly to v ss .
16 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 3-1. pin input/output circuits (1/2) type 2 in type 8-a pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd type 10-a enable type 11 pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd type 5-a input enable type 5-e pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd schmitt-triggered input with hysteresis characteristic pull-up enable data output disable in/out n-ch v ref input dd (threshold voltage) v p-ch n-ch p-ch dd v p-ch + - comparator pul-lup enable data output disable v p-ch n-ch p-ch in/out dd v dd open drain
17 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 3-1. pin input/output circuits (2/2) type 12-a type 16 pull-up enable data output disable v p-ch n-ch p-ch in/out dd v dd n-ch input enable type 13-b data output disable n-ch p-ch in/out v dd v dd rd mask option middle-high voltage input buffer p-ch analog output voltage xt1 feed back cut-off xt2 p-ch
18 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 4. memory space figure 4-1 shows the m pd78052y/78053y/78054y/78055y/78056y/78058y memory map. figure 4-1. memory map internal rom last address nnnnh relevant product name internal high-speed ram first address mmmmh m pd78052y m pd78053y m pd78054y m pd78055y m PD78056Y m pd78058y 3fffh 5fffh 7fffh 9fffh bfffh efffh fd00h fb00h special function registers (sfr) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram note3 use prohibited buffer ram 32 x 8 bits use prohibited external memory internal rom note3 data memory space program memory space ffffh ff00h feffh fee0h fedfh mmmmh mmmmh - 1 fae0h fadfh fac0h fabfh fa80h fa7fh nnnnh + 1 nnnnh 0000h use prohibited internal expanded ram 1024 x 8 bits use prohibited note2 7a7fh f800h f7ffh f400h f3ffh f000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h note1 notes 1. provided in the m pd78058y only 2. when the external device expansion function is used with the m pd78058y, set the internal rom capacity to 56 kbytes or less using the internal memory size switching register (ims). 3. the internal rom capacity and internal high-speed ram capacity depend on the products (see the next table).
19 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. ? cmos input (p00, p07) : 2 ? cmos input/output (p01 to p06, port 1 to port 5, p64 to p67, port 7, port 12, port 13) : 63 ? n-channel open-drain input/output (p60 to p63) : 4 total :69 table 5-1. port functions name pin name function port 0 p00, p07 dedicated input port pins p01 to p06 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. port 1 p10 to p17 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. port 2 p20 to p27 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. port 3 p30 to p37 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. port 4 p40 to p47 input/output port pins. input/output specifiable in 8-bit units. when used as input port pins, on-chip pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. led direct drive capability. port 6 p60 to p63 n-channel open-drain input/output port pins. input/output specifiable bit-wise. on-chip pull-up resistor can be used by mask option. led direct drive capability. p64 to p67 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. port 7 p70 to p72 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. port 12 p120 to p127 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. port 13 p130, p131 input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software.
20 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 5.2 clock generator two types of generators, a main system clock generator and a subsystem clock generator, are avaibable. the minimum instruction execution time can also be changed. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@5.0-mhz operation with main system clock) ? 122 m s (@32.768-khz operation with subsystem clock) figure 5-1. clock generator block diagram 5.3 timer/event counter 5 timer/event counter channels are incorporated. ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2. operation of timer/event counter 16-bit timer/event counter 8-bit timer/event counter watch timer watchdog timer operation mode interval timer 1 channel 2 channels 1 channel 1 channel external event counter 1 channel 2 channels function timer output 1 output 2 outputs pwm output 1 output pulse amplitude measurement 2 inputs square wave output 1 output 2 outputs one-shot pulse output 1 output interrupt source 2 2 1 1 test input 1 input xt1/p07 xt2 x1 x2 f xt f xt f xx f xx f xx f xx f xx subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit to intp0 sampling clock 2 2 2 2 3 2 4 2 prescaler selector selector f x f x 2 stop scaler 2 1
21 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 5-2. 16-bit timer/event counter block diagram figure 5-3. 8-bit timer/event counter block diagram internal bus selector selector 16-bit timer register (tm0) clear output control circuit pwm pulse output control circuit 16-bit capture/ compare register internal bus intp1 inttm00 to0/p30 inttm01 intp0 ti01/p01/intp1 watch timer output f xx f xx /2 f xx /2 2f xx 2 ti00/p00/intp0 16-bit capture/ compare register (cr01) (cr00) edge detector match match selector internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear match selector output control circuit output control circuit inttm1 to2/p32 inttm2 to1/p31 clear match selector selector selector selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) internal bus 9 11 ti1/p33 f xx /2 to f xx /2 f xx /2 to f xx /2 f xx /2 f xx /2 9 11 ti2/p34
22 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 5-4. watch timer block diagram figure 5-5. watchdog timer block diagram inttm3 intwt 5-bit counter prescaler selector selector selector selector f xx /2 f xt f w f w 7 2 f w 2 f w 2 f w 2 f w 2 f w 2 f w 2 f w 2 4 5 6 7 8 9 14 13 to 16-bit timer/ event counter control circuit 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector 4 5 6 7 8 9 11 3 f xx 2 f xx 2 f xx 2 f xx 2 f xx 2 f xx 2 f xx 2 f xx 2
23 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 5.4 clock output control circuit a clock with the following frequencies can be output as the clock output. ? 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (@5.0-mhz opera- tion with main system clock) ? 32.768 khz (@32.768-khz operation with subsystem clock) figure 5-6. clock output control circuit block diagram 5.5 buzzer output control circuit a clock with the following frequencies can be output as the buzzer output. ? 1.2 khz/2.4 khz/4.9 khz/9.8 khz (@5.0-mhz operation with main system clock) figure 5-7. buzzer output control circuit block diagram selector synchronization circuit output control circuit pcl/p35 f xx f xt f xx /2 f xx /2 f xx /2 f xx /2 f xx /2 f xx /2 f xx /2 2 3 4 5 6 7 selector output control circuit buz/p36 9 10 11 f xx /2 f xx /2 f xx /2
24 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 5.6 a/d converter an a/d converter of 8-bit resolution x 8 channels is incorporated. the following two a/d conversion operation start-up methods are available. ? hardware start ? software start figure 5-8. a/d converter block diagram tap selector intad av dd intp3 internal bus av ref0 av ss a/d conversion result register (adcr) control circuit successive approximation register (sar) edge detection circuit ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/p03 selector sample & hold circuit voltage comparator series resistor string
25 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y n = 0, 1 m = 4, 5 x = 1, 2 5.8 serial interfaces 3 channels of the clocked serial interface are incorporated. ? serial interface channel 0 ? serial interface channel 1 ? serial interface channel 2 table 5-3. types and functions of serial interface 5.7 d/a converter a d/a converter of 8-bit resolution 2 channels is available. conversion method is r-2r resistor ladder method. figure 5-9. d/a converter block diagram function serial interface channel 0 serial interface channel 1 serial interface channel 2 3-wire serial i/o made (msb/lsb first switchable) (msb/lsb first switchable) (msb/lsb first switchable) 3-wire serial i/o mode with auto- (msb/lsb first switchable) matic transmit/receive function 2-wire serial i/o mode (msb first) i 2 c bus mode (msb first) asynchronous serial interface (dedicated baud rate (uart) mode generator incorporated) internal bus selector d/a conversion value set register n (dacsn) av ref1 av ss damm inttm x dacsn write anon d/a converter mode register
26 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 5-10. serial interface channel 0 block diagram figure 5-11. serial interface channel 1 block diagram acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter stop condition/start condition/acknowledge detection circuit serial clock control circuit selector selector selector si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 intcsi0 to2 f xx /2 to f xx /2 8 internal bus interrupt request signal generator handshake control circuit buffer ram serial clock control circuit selector serial clock counter serial i/o shift register 1 (sio1) automatic data transmit/ receive address pointer (adtp) automatic data transmit/receive interval specification register (adti) 5-bit counter intcsi1 to2 8 si1/p20 so1/p21 stb/p23 busy/p24 sck1/p22 match f xx /2 to f xx /2
27 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 5-12. serial interface channel 2 block diagram 5.9 real-time output port functions data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt or external interrupt generation in order to output to off-chip. this is a real-time output function. pins used to output data to off-chip are called real-time output ports. by using a real-time output port, a signal which has no jitter can be output. this is most applicable to control stepping motors, etc. figure 5-13. real-time output port block diagram internal bus p127 p120 output latch real-time output buffer register higher 4 bits (rtbh) real-time output buffer register lower 4 bits (rtbl) real-time output port mode register (rtpm) output trigger control circuit intp2 inttm1 inttm2 rxd/si2/p70 t x d/so2/p71 asck/sck2/p72 intser intsr/intcsi2 intst 10 internal bus receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) receive control circuit direction control circuit transmit shift register (txs/sio2) transmit control circuit sck output control circuit baud rate generator f xx to f xx /2
28 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y notes 1. the default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. 6. interrupt functions and test functions 6.1 interrupt functions there are interrupt functions, 22 sources of three different types, as shown below. ? non-maskable interrupt: 1 ? maskable interrupts: 20 ? software interrupt: 1 the following table shows the interrupt source list. table 6-1. interrupt source list (1/2) default note 1 interrupt source internal/ vector basic interrupt type table configuration priority name trigger external address type note 2 non-maskable intwdt watchdog timer overflow internal 0004h (a) (watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intcsi0 end of serial interface channel 0 transfer internal 0014h (b) 9 intcsi1 end of serial interface channel 1 transfer 0016h 10 intser generation of serial interface channel 2 0018h uart receive error 11 intsr end of serial interface channel 2 uart 001ah reception intcsi2 end of serial interface channel 2 3-wire transfer 12 intst end of serial interface channel 2 uart 001ch transmission
29 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y table 6-1. interrupt source list (2/2) default note 1 interrupt source internal/ vector basic interrupt type table configuration priority name trigger external address type note 2 maskable 13 inttm3 reference time interval signal from internal 001eh (b) watch timer 14 inttm00 generation of match signal of 16-bit 0020h timer register and capture/compare register (cr00) 15 inttm01 generation of match signal of 16-bit 0022h timer register and capture/compare register (cr01) 16 inttm1 generation of match signal of 8-bit 0024h timer/event counter 1 17 inttm2 generation of match signal of 8-bit 0026h timer/event counter 2 18 intad end of conversion by a/d converter 0028h software brk brk instruction execution 003eh (e) notes 1. the default priority is a priority order when two or more maskable interrupts are generated simultaneously. 0 is the highest order and 18, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively.
30 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 6-1. interrupt function basic configuration(1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) internal bus priority control circuit vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request mk ie pr isp if priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detection circuit sampling clock internal bus standby release signal interrupt request
31 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y figure 6-1. interrupt function basic configuration(2/2) (d) external maskable interrupt (except intp0) priority control circuit vector table address generator internal bus interrupt request mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0 and intm1) edge detection circuit internal bus standby release signal interrupt request (e) software interrupt if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag
32 m pd78052 y , 78053 y , 78054 y , 78055 y , 78056 y , 78058y 6.2 t es t f u n c t ions there are two test functions as shown in table 6-2. table 6-2. test input source list figure 6-2. test function basic configuration i f : test input flag m k : test mask flag mk internal bus if standby release signal test input test input source internal/external name trigger intwt watch timer overflow internal intpt4 port 4 falling edge detection external
33 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation) subsystem clock operation note halt mode note (clock supply to cpu is stopped, oscillation) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css=1 css=0 7. external device expansion functions the external device expansion functions connect external devices to areas other than the internal rom, ram, and sfr. ports 4 to 6 are used for external device connection. 8. standby function there are the following two standby functions to reduce the system current consumption. ? halt mode : the cpu operating clock is stopped. the average current consumption can be reduced by intermittent operation in combination with the normal operating mode. ? stop mode : the main system clock oscillation is stopped. the whole operation by the main system clock is stopped, so that the system operates with ultra-low current consumption using only the subsystem clock. figure 8-1. standby function note the current consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) of processor clock control register (pcc) to stop the main system clock. the stop instruction cannot be used. caution when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. 9. reset function there are the following two reset methods. ? external reset input by reset pin ? internal reset by watchdog time runaway time detection
34 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 10. instruction set (1) 8-bit instructions mov, xch, add addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov mov push pop [de] ror4 [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
35 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y (2) 16-bit instructions mov, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de, or hl (3) bit manipulate instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw decw push pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1
36 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br bc bnc bz bnz bt bf btclr dbnz
37 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 11. electrical specifications absolute maximum ratings (t a = 25 c) note the r.m.s. should be calculated as follows: [r.m.s.] = [peak value] ? duty caution if any of the parameters exceed the absolute maximum ratings, even momentarily, device reliability may be impaired. the absolute maximum ratings are values that may physically damage the product. be sure to use the product within the ratings. remark the characteristics of dual-function pins and port pins are the same unless otherwise specified. parameter symbol test conditions rating unit supply voltage v dd C0.3 to +7.0 v av dd C0.3 to v dd + 0.3 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, C0.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open-drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss C 0.3 to av ref0 + 0.3 v output i oh 1 pin C10 ma current high p01 to p06, p30 to p37, p56, p57, p60 to p67, C15 ma p120 to p127 total p10 to p17, p20 to p27, p40 to p47, p50 to p55, C15 ma p70 to p72, p130, p131 total output i ol note 2 1 pin peak value 30 ma current low r.m.s. value 15 ma p50 to p55 total peak value 100 ma r.m.s. value 70 ma p56, p57, p60 to p63 total peak value 100 ma r.m.s. value 70 ma p10 to p17, p20 to p27, p40 to p47, peak value 50 ma p70 to p72, p130, p131 total r.m.s. value 20 ma p01 to p06, p30 to p37, p64 to p67, peak value 50 ma p120 to p127 total r.m.s. value 20 ma operating ambient t a C40 to +85 c temperature storage t stg C65 to +150 c temperature
38 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y main system clock oscillation circuit characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid adverse effects from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. x1 ic x2 c2 c1 r1 x1 x2 pd74hcu04 recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillator frequency (fx) note 1 oscillation stabilization time note 2 oscillator frequency (fx) note 1 oscillation stabilization time note 2 x1 input frequency (fx) note 1 x1 input high/low level width (t xh , t xl ) min. 1.0 1.0 1.0 85 test conditions v dd = oscillator voltage range after v dd reaches oscil- lation voltage range min. v dd = 4.5 to 6.0 v x1 ic x2 c2 c1
39 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y subsystem clock oscillation circuit characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches min. in the oscillation voltage range. cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as vss. ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillation circuit is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. when using the subsystem clock, pay special attention to wiring as described above. xt2 xt1 ic c4 c3 r2 xt1 xt2 min. 32 32 5 resonator crystal resonator external clock parameter oscillator frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high/low level width (t xth , t xtl ) test conditions v dd = 4.5 to 6.0 v typ. 32.768 1.2 max. 35 2 10 100 15 unit khz s khz m s recommended circuit
40 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y recommended oscillator constant (1) m pd78052y, 78053y, 78054y, 78055y, 78056y main system clock: ceramic resonator (t a = e40 to +85 c) main system clock: crystal resonator (t a = e10 to +70 c) subsystem clock: crystal resonator (t a = e10 to +70 c) frequency recommended oscillator manufacturer product name circuit consonant voltage range remarks (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csa5.00mg 5.00 30 30 2.0 6.0 co., ltd. cst5.00mgw 5.00 on-chip on-chip 2.0 6.0 capacitor on chip kyocera kbr-5.0msa 5.00 33 33 2.0 6.0 lead type corp. kbr-5.0mks 5.00 on-chip on-chip 2.0 6.0 capacitor on chip, lead type kbr-5.0mws 5.00 on-chip on-chip 2.0 6.0 capacitor on chip, lead type pbrc 5.00a 5.00 33 33 2.0 6.0 chip type tdk corp. ccr4.0mc3 4.00 on-chip on-chip 2.0 6.0 capacitor on chip ccr5.0mc3 5.00 on-chip on-chip 2.0 6.0 capacitor on chip c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) daishinku corp. smd-49 3.579545 27 27 1.5 2.0 6.0 recommended circuit constant oscillator voltage range product name c3 (pf) c4 (pf) r2 (k w ) min. (v) max. (v) daishinku corp. dt-38 32.768 27 20 330 2.0 6.0 (1ta252e00) recommended circuit constant oscillator voltage range product name frequency (mhz) frequency (mhz) manufacturer manufacturer caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. however, they do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used.
41 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y (2) m pd78058y main system clock: ceramic resonator (t a = e40 to +85 c) capacitance (t a = 25 c, v dd = v ss = 0 v) remark the characteristics of the dual-function pins and port pins are the same unless otherwise specified. frequency recommended oscillator manufacturer product name circuit consonant voltage range remarks (mhz) c1 (pf) c2 (pf) min. (v) max. (v) kyocera pbrc4.19a 4.19 33 33 2.0 6.0 corp. pbrc4.19b 4.19 on-chip on-chip 2.0 6.0 capacitor on chip kbr-4.19msa 4.19 33 33 2.0 6.0 kbr-4.19mks 4.19 on-chip on-chip 2.0 6.0 capacitor on chip pbrc4.91a 4.91 33 33 2.0 6.0 pbrc4.91b 4.91 on-chip on-chip 2.0 6.0 capacitor on chip kbr-4.91msa 4.91 33 33 2.0 6.0 kbr-4.91mks 4.91 on-chip on-chip 2.0 6.0 capacitor on chip parameter symbol test conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance measured pins retured to 0 v. input/output c io f = 1 mhz p01 to p06, p10 to p17, 15 pf capacitance measured pins retured p20 to p27, p30 to p37, to 0 v. p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. however, they do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used.
42 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y dc characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol test conditions min. typ. max unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 6.0 v 0.7 v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p120 to p127, 0.8 v dd v dd v p130, p131 v ih2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 6.0 v 0.8 v dd v dd v p33, p34, p70, p72, reset 0.85 v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 6.0 v 0.7 v dd 15 v (n-ch open-drain) 0.8 v dd 15 v v ih4 x1, x2 v dd = 2.7 to 6.0 v v dd C 0.5 v dd v v dd C 0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 6.0 v 0.8 v dd v dd v 2.7 v v dd < 4.5 v 0.9 v dd v dd v 2.0 v v dd < 2.7 v note 0.9 v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 6.0 v 0 0.3 v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p120 to p127, 0 0.2 v dd v p130, p131 v il2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 6.0 v 0 0.2 v dd v p33, p34, p70, p72, reset 0 0.15 v dd v v il3 p60 to p63 4.5 v v dd 6.0 v 0 0.3 v dd v 2.7 v v dd < 4.5 v 0 0.2 v dd v 0 0.1 v dd v v il4 x1, x2 v dd = 2.7 to 6.0 v 0 0.4 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 6.0 v 0 0.2 v dd v 2.7 v v dd < 4.5 v 0 0.1 v dd v 2.0 v v dd < 2.7 v note 0 0.1 v dd v output voltage, v oh v dd = 4.5 to 6.0 v, i oh = C1 ma v dd C 1.0 v high i oh = C100 m av dd C 0.5 v output voltage, v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 6.0 v, 0.4 2.0 v low i ol = 15 ma p01 to p06, p10 to p17, p20 to p27, v dd = 4.5 to 6.0 v, 0.4 v p30 to p37, p40 to p47, p64 to p67, i ol = 1.6 ma p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 6.0 v, 0.2 v dd v open-drain, pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v note for use the p07/xt1 pin as p07, input the reverse phase of p07 to the xt2 pin. remark the characteristics of dual-function pins and port pins are the same unless otherwise specified.
43 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y dc characteristics (t a = e40 to +85 c, v dd = 2.7 to 6.0 v) notes 1. if no pull-up resistor is connected in p60 to p63 (specified with mask option), a C200 m a (max.) low-level input leak current flows only during the 1.5-clock interval (no wait interval) during which a read instruction is executed for port 6 (p6) and port mode register (pm6). the leak current is C3 m a (max.) at all times other than the 1.5-clock interval during which the read instruction is executed. 2. a software pull-up resistor can be used only in the range of v dd = 2.7 to 6.0 v. remark the characteristics of dual-function pins and port pins are the same unless otherwise specified. parameter symbol test conditions min. typ. max unit input leakage i lih1 v in = v dd p00 to p06, p10 to p17, p20 to p27, 3 m a current, high p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakage i lil1 v in = 0 v p00 to p06, p10 to p17, p20 to p27, C3 m a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60 to p63 C3 note 1 m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low mask option r 1 v in = 0 v, p60 to p63 20 40 90 k w pull-up resistor software pull-up r 2 v in = 0 v, p01 to p06, 4.5 v v dd 6.0 v 15 40 90 k w resistor note 2 p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, 2.7 v v dd < 4.5 v 20 500 k w p70 to p72, p120 to p127, p130, p131
44 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y dc characteristics (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) notes 1. the on-chip pull-up resistor, av ref0 , av ref1 , av dd current, and port current are not included. 2. operation with main system clock f xx = f x /2 (when oscillation mode selection register (osms) is set to 00h) 3. operation with main system clock f xx = f x (when osms is set to 01h) 4. when the main system clock operation is halted. 5. operating in high-speed mode (when the processor clock control register (pcc) is set to 00h.) 6. operating in low-speed mode (when pcc is set to 04h) parameter symbol test conditions min. typ. max unit power supply i dd1 5.0 mhz crystal oscillation v dd = 5.0 v 10 % note 1 412ma current note 5 operating mode v dd = 3.0 v 10 % note 2 0.6 1.8 ma (f xx = 2.5 mhz) note 3 v dd = 2.2 v 10 % note 2 0.35 1.05 ma 5.0 mhz crystal oscillation v dd = 5.0 v 10 % note 1 6.5 19.5 ma operating mode (f xx = 5.0 mhz) note 4 v dd = 3.0 v 10 % note 2 0.8 2.4 ma i dd2 5.0 mhz crystal oscillation v dd = 5.0 v 10 % 1.4 4.2 ma halt mode v dd = 3.0 v 10 % 0.5 1.5 ma (f xx = 2.5 mhz) note 3 v dd = 2.2 v 10 % 280 840 m a 5.0 mhz crystal oscillation v dd = 5.0 v 10 % 1.6 4.8 ma halt mode (f xx = 5.0 mhz) note 4 v dd = 3.0 v 10 % 0.65 1.95 ma i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10 % 60 120 m a operating mode note 6 v dd = 3.0 v 10 % 32 64 m a v dd = 2.2 v 10 % 24 48 m a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10 % 25 55 m a halt mode note 6 v dd = 3.0 v 10 % 5 15 m a v dd = 2.2 v 10 % 2.5 12.5 m a i dd5 xt1 = v dd v dd = 5.0 v 10 % 1 30 m a stop mode v dd = 3.0 v 10 % 0.5 10 m a when feedback resistor is used v dd = 2.2 v 10 % 0.3 10 m a i dd6 xt1 = v dd v dd = 5.0 v 10 % 0.1 30 m a stop mode v dd = 3.0 v 10 % 0.05 10 m a when feedback resistor is unused v dd = 2.2 v 10 % 0.05 10 m a
45 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 2.0 to 6.0 v) notes 1. main system clock f xx = f x /2 operation (when an oscillation mode selection register (osms) is set to 00h) 2. main system clock f xx = f x operation (when osms is set to 01h) 3. on an external clock. when a crystal resonator is used, the minimum value is 114 m s. 4. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock selection register, fsam is selectable between f xx /2 n , f xx /32, f xx /64, and f xx /128 (when n= 0 to 4). parameter symbol test conditions min. typ. max. unit cycle time t cy operating on main system clock v dd = 2.7 to 6.0 v 0.8 64 m s (min. instruction (f xx = 2.5 mhz) note 1 2.2 64 m s execution time) operating on main system clock 4.5 v v dd 6.0 v 0.4 32 m s (f xx = 5.0 mhz) note 2 2.7 v v dd < 4.5 v 0.8 32 m s operating on sub system clock 40 note 3 122 125 m s ti00 input t tih00, 3.5 v v dd 6.0 v 2/f sam + 0.1 note4 m s high-/low-level width t til00 2.7 v v dd < 3.5 v 2/f sam + 0.2 note4 m s 2/f sam + 0.5 note4 m s ti01 input t tih01 ,v dd = 2.7 to 6.0 v 10 m s high-/low-level width t til01 20 m s ti1, ti2 f ti1 v dd = 4.5 to 6.0 v 0 4 mhz input frequency 0 275 khz ti1, ti2 input t tih1 ,v dd = 4.5 to 6.0 v 100 ns high-/low-level width t til1 1.8 m s interrupt request t inth , intp0 3.5 v v dd 6.0 v 2/f sam + 0.1 note4 m s input high-/ t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note4 m s low-level width 2/f sam + 0.5 note4 m s intp1 to intp6, kr0 to kr7 v dd = 2.7 to 6.0 v 10 m s 20 m s reset low t rsl v dd = 2.7 to 6.0 v 10 m s level width 20 m s
46 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y t cy vs v dd (at f xx = f x main system clock operation) t cy vs v dd (at f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 cycle time t cy [s] 123456 supply voltage v dd [v] 60 10 2.0 1.0 0.5 0.4 0 cycle time t cy [s] 123456 supply voltage v dd [v] operation guaranteed range operation guaranteed range
47 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y (2) read/write operation (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = e40 to +85 c, v dd = 4.5 to 6.0 v) parameter symbol test conditions min. max. unit astb high-level width t asth 0.85t cy C 50 ns address setup time t ads 0.85t cy C 50 ns address hold time t adh 50 ns data input time from address t add1 (2.85 + 2n)t cy C 80 ns t add2 (4 + 2n)t cy C 100 ns data input time from rd t rdd1 (2 + 2n)t cy C 100 ns t rdd2 (2.85 + 2n)t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy C 60 ns t rdl2 (2.85 + 2n)t cy C 60 ns wait input time from rd t rdwt1 0.85t cy C 50 ns t rdwt2 2t cy C 60 ns wait input time from wr t wrwt 2t cy C 60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy C 100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n)t cy C 60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy + 20 ns astb - delay time from t rdast 0.85t cy C 10 1.15t cy + 20 ns rd - in external fetch address hold time from t rdadh 0.85t cy C 50 1.15t cy + 50 ns rd - in external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t rdwd 050ns address hold time from wr - t wradh 0.85t cy 1.15t cy + 40 ns rd - delay time from wait - t wtrd 1.15t cy + 40 3.15t cy + 40 ns wr - delay time from wait - t wtwr 1.15t cy + 30 3.15t cy + 30 ns remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to 0 3. t cy = t cy /4 4. n indicates number of waits.
48 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. max. unit astb high-level width t asth v dd = 2.7 to 6.0 v t cy C 80 ns t cy C 150 ns address setup time t ads v dd = 2.7 to 6.0 v t cy C 80 ns t cy C 150 ns address hold time t adh v dd = 2.7 to 6.0 v 0.4t cy C 10 ns 0.37t cy C 40 ns data input time from address t add1 v dd = 2.7 to 6.0 v (3 + 2n)t cy C 160 ns (3 + 2n)t cy C 320 ns t add2 v dd = 2.7 to 6.0 v (4 + 2n)t cy C 200 ns (4 + 2n)t cy C 300 ns data input time from rd t rdd1 v dd = 2.7 to 6.0 v (1.4 + 2n)t cy C 70 ns (1.37 + 2n)t cy C 120 ns t rdd2 v dd = 2.7 to 6.0 v (2.4 + 2n)t cy C 70 ns (2.37 + 2n)t cy C 120 ns read data hold time t rdh 0ns rd low-level width t rdl1 v dd = 2.7 to 6.0 v (1.4 + 2n)t cy C 20 ns (1.37 + 2n)t cy C 20 ns t rdl2 v dd = 2.7 to 6.0 v (2.4 + 2n)t cy C 20 ns (2.37 + 2n)t cy C 20 ns wait input time from rd t rdwt1 v dd = 2.7 to 6.0 v t cy C 100 ns t cy C 200 ns t rdwt2 v dd = 2.7 to 6.0 v 2t cy C 100 ns 2t cy C 200 ns wait input time from wr t wrwt v dd = 2.7 to 6.0 v 2t cy C 100 ns 2t cy C 200 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds v dd = 2.7 to 6.0 v (2.4 + 2n)t cy C 60 ns (2.37 + 2n)t cy C 100 ns write data hold time t wdh 20 ns wr low-level width t wrl v dd = 2.7 to 6.0 v (2.4 + 2n)t cy C 20 ns (2.37 + 2n)t cy C 20 ns rd delay time from astb t astrd v dd = 2.7 to 6.0 v 0.4t cy C 30 ns 0.37t cy C 50 ns wr delay time from astb t astwr v dd = 2.7 to 6.0 v 1.4t cy C 30 ns 1.37t cy C 50 ns (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) (1/2) remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to 0 3. t cy = t cy /4 4. n indicates the number of waits.
49 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. max. unit astb - delay time from t rdast t cy C 10 t cy + 20 ns rd - in external fetch address hold time from t rdadh t cy C 50 t cy + 50 ns rd - in external fetch write data output time from rd - t rdwd v dd = 2.7 to 6.0 v 0.4t cy C 20 ns 0.37t cy C 40 ns write data output time from wr t wrwd v dd = 2.7 to 6.0 v 0 60 ns 0 120 ns address hold time from wr - t wradh v dd = 2.7 to 6.0 v t cy t cy + 60 ns t cy t cy + 120 ns rd - delay time from wait - t wtrd v dd = 2.7 to 6.0 v 0.6t cy + 180 2.6t cy + 180 ns 0.63t cy + 350 2.63t cy + 350 ns wr - delay time from wait - t wtwr v dd = 2.7 to 6.0 v 0.6t cy + 120 2.6t cy + 120 ns 0.63t cy + 240 2.63t cy + 240 ns (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) (1/2) remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to 0 3. t cy = t cy /4 4. n indicates number of waits.
50 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck0 high-/low-level t kh1 , t kl1 v dd = 4.5 to 6.0 v t kcy1 /2 C 50 ns width t kcy1 /2 C 100 ns si0 setup time t sik1 4.5 v v dd 6.0 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si0 hold time (from t ksi1 400 ns sck0 - ) so0 output delay time t kso1 c = 100 pf note 300 ns from sck0 parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck0 high-/low-level t kh2 , t kl2 4.5 v v dd 6.0 v 400 ns width 2.7 v v dd < 4.5 v 800 ns 1600 ns si0 setup time (to t sik2 100 ns sck0 - ) si0 hold time (from t ksi2 400 ns sck0 - ) so0 output delay time t kso2 c = 100 pf note 300 ns from sck0 sck0 rise, fall time t r2 , t f2 when using external device 160 ns expansion function when not using external device 1000 ns expansion function (3) serial interface (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) note c is the load capacitance of sck0, so0 output line. (ii) 3-wire serial i/o mode (sck0... external clock input) note c is the load capacitance of so0 output line.
51 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 2.7 to 6.0 v 1600 ns 3200 ns sck0 high-level width t kh4 v dd = 2.7 to 6.0 v 650 ns 1300 ns sck0 low-level width t kl4 v dd = 2.7 to 6.0 v 800 ns 1600 ns sb0, sb1 setup time t sik4 100 ns (to sck0 - ) sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) sb0, sb1 output delay t kso4 r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns time from sck0 c = 100 pf note 0 500 ns sck0 rise, fall time t r4 , t f4 when using external device 160 ns expansion function when not using external device 1000 ns expansion function parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 r = 1 k w ,v dd = 2.7 to 6.0 v 1600 ns c = 100 pf note 3200 ns sck0 high-level width t kh3 v dd = 2.7 to 6.0 v t kcy3 /2 C 160 ns t kcy3 /2 C 190 ns sck0 low-level width t kl3 v dd = 4.5 to 6.0 v t kcy3 /2 C 50 ns t kcy3 /2 C 100 ns sb0, sb1 setup time t sik3 4.5 v v dd 6.0 v 300 ns (to sck0 - ) 2.7 v v dd < 4.5 v 350 ns 400 ns sb0, sb1 hold time t ksi3 600 ns (from sck0 - ) sb0, sb1 output delay t kso3 0 300 ns time from sck0 (iii) 2-wire serial i/o mode (sck0... internal clock output) note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output line. (iv) 2-wire serial i/o mode (sck0... external clock input) note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output line.
52 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. typ. max. unit scl cycle time t kcy5 r = 1 k w v dd = 2.7 to 6.0 v 10 m s c = 100pf note 20 m s scl high-level width t kh5 v dd = 2.7 to 6.0 v t kcy5 C 160 ns t kcy5 C 190 ns scl low-level width t kl5 v dd = 4.5 to 6.0 v t kcy5 C 50 ns t kcy5 C 100 ns sda0, sda1 setup time t sik5 v dd = 2.7 to 6.0 v 200 ns (to scl - ) 300 ns sda0, sda1 hold time t ksi5 0ns (to scl ) sda0, sda1 output t kso5 v dd = 4.5 to 6.0 v 0 300 ns delay time from scl 0 500 ns scl -? sda0, sda1 t ksb 200 ns or scl -? sda0, sda1 - sda0, sda1 ? scl t sbk 400 ns sda0, sda1 high-level t sbh 500 ns width (v) i 2 c bus mode (scl...internal clock output) parameter symbol test conditions min. typ. max. unit scl cycle time t kcy6 1000 ns scl high-/low-level width t kh6 , t kl6 400 ns sda0, sda1 setup time t sik6 200 ns (to scl - ) sda0, sda1 hold time t ksi6 0ns (to scl ) scl ? sda0, sda1 t kso6 r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns output delay time c = 100 pf note 0 500 ns scl -? sda0, sda1 t ksb 200 ns or scl -? sda0, sda1 - sda0, sda1 ? scl t sbk 400 ns sda0, sda1 high-level t sbh 500 ns width scl rise, fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output line. (vi) i 2 c bus mode (scl...external clock input) note r and c are the load resistance and load capacitance of the sda0, sda1 output line.
53 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh7 , t kl7 v dd = 4.5 to 6.0 v t kcy7 /2 C 50 ns width t kcy7 /2 C 100 ns si1 setup time t sik7 4.5 v v dd 6.0 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si1 hold time t ksi7 400 ns (from sck1 - ) so1 output delay time t kso7 c = 100 pf note 300 ns from sck1 note c is the load capacitance of the sck1 and so1 output lines. (ii) 3-wire serial i/o mode (sck1... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level t kh8 , t kl8 4.5 v v dd 6.0 v 400 ns width 2.7 v v dd < 4.5 v 800 ns 1600 ns si1 setup time t sik8 100 ns (to sck1 - ) si1 hold time t ksi8 400 ns (from sck1 - ) so1 output delay t kso8 c = 100 pf note 300 ns time from sck1 sck1 rise, fall time t r8 , t f8 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note c is the load capacitance of the so1 output line.
54 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level width t kh10 , 4.5 v v dd 6.0 v 400 ns t kl10 2.7 v v dd < 4.5 v 800 ns 1600 ns si1 setup time (to sck1 - )t sik10 100 ns si1 hold time (from sck1 - )t kis10 400 ns so1 output delay time from sck1 t kso10 c = 100 pf note 300 ns sck1 rise, fall time t r10 , when using external 160 ns t f10 device expansion function when not using external 1000 ns device expansion function parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck1 high-/low-level width t kh9 ,v dd = 4.5 to 6.0 v t kcy9 /2 C 50 ns t kl9 t kcy9 /2 C 100 ns si1 setup time (to sck1 - )t sik9 4.5 v v dd 6.0 v 100 ns 2.7 v v dd < 4.5 v 150 ns 300 ns si1 hold time (from sck1 - )t ksi9 400 ns so1 output delay time from sck1 t kso9 c = 100 pf note 300 ns stb - from sck1 - t sbd t kcy9 /2 C 100 t kcy9 /2 + 100 ns strobe signal high-level width t sbw v dd = 2.7 to 6.0v t kcy9 C 30 t kcy9 + 30 ns t kcy9 C 60 t kcy9 + 60 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 6.0 v 100 ns (from busy signal detection timing) 2.7 v v dd < 4.5 v 150 ns 200 ns sck1 from busy inactive t sps 2t kcy9 ns note c is the load capacitance of the sck1, so1 output line. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1...external clock input) note c is the load capacitance of the so1 output line. (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1...internal clock output)
55 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy11 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns sck2 high-/low-level t kh11 , v dd = 4.5 to 6.0 v t kcy11 /2 C 50 ns width t kl11 t kcy11 /2 C 100 ns si2 setup time t sik11 4.5 v v dd 6.0 v 100 ns (to sck2 - ) 2.7 v v dd < 4.5 v 150 ns 300 ns si2 hold time t ksi11 400 ns (to sck2 - ) so2 output delay time t kso11 c = 100 pf note 300 ns from sck2 (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2... internal clock output) note c is the load capacitance of the sck2, so2 output line. (ii) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit asck cycle time t kcy12 4.5 v v dd 6.0 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 3200 ns asck high-/low-level t kh12 , 4.5 v v dd 6.0 v 400 ns width t kl12 2.7 v v dd < 4.5 v 800 ns 1600 ns transfer rate 4.5 v v dd 6.0 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 9766 bps asck rise, fall time t r12 , t f12 v dd = 4.5 to 6.0 v, 1000 ns when not using external device expansion function. 160 ns parameter symbol test conditions min. typ. max. unit transfer rate 4.5 v v dd 6.0 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 19531 bps (iii) uart mode (external clock input)
56 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y ac timing test point (excluding x1, xt1 input) clock timing ti timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 1/f ti1 t til1 t tih1 ti1, ti2 t til00 , t til01 t tih00 , t tih01 ti00, ti01 t xl t xh 1/f x v ih4 (min.) v il4 (max.) v ih5 (min.) v il5 (max.) t xtl t xth 1/f xt x1 input xt1 input
57 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y read/write operation external fetch (no wait) : t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address operation code lower 8-bit address t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address operation code lower 8-bit address external fetch (wait insertion) :
58 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y external data access (no wait) : t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wdwr t astwr t wradh higher 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwd t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wdwr t astwr t wradh higher 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd external data access (wait insertion) :
59 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y serial transfer timing 3-wire serial i/o mode : 2-wire serial i/o mode : t f4 t r4 sck0 sb0, sb1 t kl3, 4 t kh3, 4 t kcy3, 4 t ksi3, 4 t sik3, 4 t kso3, 4 i 2 c bus mode: t f6 t r6 t kcy5, 6 t kl5, 6 t ksi5, 6 t kh5, 6 t kso5, 6 t sik5, 6 t ksb t sbk t ksb t sbh t sbk scl sda0, sda1 sck0 to sck2 t rn t klm t kcym t khm t fn si0 to si2 input data t ksim t sikm output data t ksom so0 to so2 m = 1, 2, 7, 8, 11 n = 2, 8
60 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 3-wire serial i/o mode with automatic transmit/receive function : 3-wire serial i/o mode with automatic transmit/receive function (busy processing) : note the signal is not actually driven low here; it is shown as such to indicate the timing. stb sck1 si1 so1 d2 d1 d0 d2 d1 d0 d7 d7 t sik9, 10 t ksi9, 10 t kso9, 10 t kh9, 10 t f10 t r10 t kl9, 10 t kcy9, 10 t sbd t sbw t bys sck1 t sps busy (active high) 789 note 10 note 10+n note 1 t byh uart mode (external clock input) : t kcy12 t kh12 t kl12 t f12 t r12 asck
61 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y resolution overall error settling time output resistance analog reference voltage av ref1 current note overall error excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency d/a converter characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v, av ss = v ss = 0 v) a/d converter characteristics (t a = e40 to +85 c, av dd = v dd = 2.0 to 6.0 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit 8 8 8 bit 2.7 v av ref0 av dd 0.6 % 2.0 v av ref0 < 2.7 v 1.4 % t conv 19.1 200 m s t samp 12/fxx m s v ian av ss av ref0 v av ref0 2.0 av dd v r airef0 4 14 k w resolution overall error note conversion time sampling time analog input voltage reference voltage resistance between av ref0 and av ss notes 1. r and c denote d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel dacs0, dacs1: d/a conversion value setting register. parameter symbol test conditions min. typ. max. unit 8 bit r = 2 m w note1 1.2 % r = 4 m w note1 0.8 % r = 10 m w note1 0.6 % c=30pf 4.5 v av ref1 6.0 v 10 m s note1 2.7 v av ref1 < 4.5 v 15 m s 2.0 v av ref1 < 2.7 v 20 m s r o dacs0, dacs1 = 55h note 2 10 k w av ref1 2.0 v dd v i ref1 note2 1.5 ma
62 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y parameter symbol test conditions min. typ. max. unit data retention power v dddr 1.8 6.0 v supply voltage data retention i dddr v dddr = 1.8 v 0.1 10 m a power supply subsystem clock stop and feedback resistor current disconnected release signal set time t srel 0 m s oscillation stabiliation t wait release by reset 2 17 /fx ms wait time release by interrupt request note ms data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time selection register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
63 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y interrupt request input timing t rsl reset t intl t inth intp0 to intp6 reset input timing
64 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 12. characteristic curves (reference value) i dd vs v dd (fx = fxx = 5.0 mhz) (t a = 25 c) pcc = 01h pcc = 00h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = b0h halt (x1 stop, xt1 oscillation) 0 23456789 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 suppl y volta g e v dd ( v ) supply current i dd (ma) 0.5
65 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y i dd vs v dd (fx = 5.0 mhz, fxx = 2.5 mhz) (t a = 25 c) pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = b0h halt (x1 stop, xt1 oscillation) 0 23456789 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 supply voltage v dd (v) supply current i dd (ma) pcc = 04h 0.5
66 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 13. package drawing remark dimensions and materials of es product are the same as those of mass-production products. 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.00?.20 0.551 +0.009 ?.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 17.20?.20 0.677?.008 g 0.825 0.032 h 0.32?.06 0.013 +0.002 ?.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60?.20 0.063?.008 l 0.80?.20 0.031 +0.009 ?.008 n 0.10 0.004 p 1.40?.10 0.055?.004 q 0.125?.075 0.005?.003 r3 3 +7 ? +7 ? d 17.20?.20 0.677?.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end
67 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y 14. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for a detailed description of recommended soldering conditions, refer to the information document semiconduc- tor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 14-1. surface mounting type soldering conditions m pd78052ygc-xxx-8bt : 80-pin plastic qfp (14 14 mm) m pd78053ygc-xxx-8bt : 80-pin plastic qfp (14 14 mm) m pd78054ygc-xxx-8bt : 80-pin plastic qfp (14 14 mm) m pd78055ygc-xxx-8bt : 80-pin plastic qfp (14 14 mm) m PD78056Ygc-xxx-8bt : 80-pin plastic qfp (14 14 mm) m pd78058ygc-xxx-8bt : 80-pin plastic qfp (14 14 mm) infrared reflow vps wave soldering partial heating package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: twice max. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: twice max. solder bath temperature : 260 c max., duration : 10 sec. max., number of times: once, preheating temperature : 120 c max. (package surface temperature) pin temperature: 300 c max. duration: 3 sec. max. (per pin row) soldering conditions soldering method ir35-00-2 vp15-00-2 ws60-00-1 recommended condition symbol caution avoid as much as possible combining two or more soldering methods (except for the partial heating method).
68 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y appendix a. development tools the following development tools are available for system development using m pd78054y subseries. language processing software prom writing tools ra78k/0 notes 1, 2, 3, 4 78k/0 series common assembler package cc78k/0 notes 1, 2, 3, 4 78k/0 series common c compiler package df78054 notes 1, 2, 3, 4 device file common to m pd78054 subseries cc78k/0-l notes 1, 2, 3, 4 78k/0 series common c compiler library source file pg-1500 prom programmer pa-78p054gc programmer adapters connected to pg-1500 pa-78p054kk-t pg-1500 controller notes 1, 2 pg-1500 control program ie-78000-r in-circuit emulator common to 78k/0 series ie-78000-r-a in-circuit emulator common to 78k/0 series (for integrated debugger) ie-78000-r-bk break board common to 78k/0 series ie-780308-r-em emulation board common to m pd780308 subseries ie-78000-r-sv3 interface adapter and cable when using ews for the host machine (for ie-78000-r-a) ie-78000-98-if-b interface adapter when using the pc-9800 series (except for notebook computers) for the host machine (for ie-78000-r-a) ie-78000-98n-if interface adapter and cable when using the pc-9800 series notebook computers for the host machine (for ie-78000-r-a) ie-78000-pc-if-b interface adapter when using ibm/pc at? and its compatibles for the host machine (for ie-78000-r-a) ep-78230gc-r emulation probe common to m pd78234 subseries ev-9200gc-80 socket to be mounted in the target system board manufactured for 80-pin plastic qfp (gc-8bt type) sm78k0 notes 5, 6, 7 system simulator common to 78k/0 series id78k0 notes 4, 5, 6, 7 integrated debugger for ie-78000-r-a sd78k/0 notes 1, 2 screen debugger for ie-78000-r df78054 notes 1, 2, 4, 5, 6, 7 device file common to m pd78054 subseries debugging tools notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at and compatible computer (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sun os tm ) based, ews4800 series (ews-ux/ v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatible computer (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based
69 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y notes 1. pc-9800 series (ms-dos) based 2. ibm pc/at and its compatible computers (pc dos/ibm dos/ms-dos) based 3. hp9000 series 300 (hp-ux) based 4. hp9000 series 700 (hp-ux) based, sparcstation (sun os) based, ews4800 series (ews-ux/v) based 5. ibm pc/at and its compatible computers (pc dos/ibm dos/ms-dos + windows) based remarks 1. for third party development tools, see the 78k/0 series selection guide (u11126e) . 2. ra78k/0, cc78k/0, sm78k0, id78k0, sd78k/0, and rx78k/0 are used in combination with df78054. fuzzy inference development support system fe9000 note 1 / fe9200 note 5 fuzzy knowledge data creation tool ft9080 note 1 / ft9085 note 2 translator fi78k0 notes 1, 2 fuzzy inference module fd78k0 notes 1, 2 fussy inference debugger rx78k/0 notes 1, 2, 3, 4 real-time os for 78k/0 series mx78k0 notes 1, 2, 3, 4 os for 78k/0 series real-time os
70 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y document name document no. document no. (english) (japanese) ra78k series assembler package operation eeu-1399 eeu-809 language eeu-1404 eeu-815 ra78k series structured assembler preprocessor eeu-1402 u12323j cc78k0 c assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j cc78k series c compiler operation eeu-1280 eeu-656 language eeu-1284 eeu-655 cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k/0 c compiler application note programming know-how eea-1208 eea-618 cc78k series library source file u12322e u12322j pg-1500 prom programmer u11940e u11940j pg-1500 controller pc-9800 series (ms-dos) based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos) based u10540e eeu-5008 ie-78000-r u11376e u11376j ie-78000-r-a u10057e u10057j ie-78000-r-bk eeu-1427 eeu-867 ie-780308-r-em u11362e u11362j ep-78230 eeu-1515 eeu-985 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications sd78k/0 screen debugger introduction C eeu-852 pc-9800 series (ms-dos) based reference C u10952j sd78k/0 screen debugger introduction u10539e eeu-5024 ibm pc/at (pc dos) based reference u11279e u11279j id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539e u11539j id78k0 integrated debugger windows based guide u11649e u11649j document name document no. document no. (english) (japanese) m pd78052y,78053y, 78054y, 78055y, 78056y, 78058y data sheet this document u10906j m pd78p058y data sheet u10907e u10907j m pd78054 and m pd78054y subseries users manual ieu-1356 u11747j 78k/0 series users manual instructions u12326e u12326j 78k/0 series instruction set C u10904j 78k/0 series instruction table C u10903j m pd78054y special function register table C u10087j 78k/0 series application note basics (iii) u10182e u10182j appendix b. related documents device related documents development tool related documents (users manual) caution the above documents are subject to change without notice. for design purpose, etc., be sure to use the latest document.
71 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y document name document no. document no. (english) (japanese) ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor device c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to quality assurance for semiconductor devices mei-1202 c11893j microcomputer-related product guide, third party products C u11416j document name document no. document no. (english) (japanese) 78k/0 series real time os basics u11537e u11537j installation u11536e u11536j mx78k0: os for 78k/0 series basic u12257e u12257j fuzzy knowledge data creation tools eeu-1438 eeu-829 78k/0, 78k/ii, 87ad series fuzzy inference development support system translator eeu-1444 eeu-862 78k/0 series fuzzy inference development support system fuzzy inference module eeu-1441 eeu-858 78k/0 series fuzzy inference development support system fuzzy inference debugger eeu-1458 eeu-921 embedded software documents (users manual) other documents caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents.
72 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
73 m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78052y, 78053y, 78054y, 78055y, 78056y, 78058y the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental licence, the need for which must be judged by the customer. the export or re- export of this product from a country other than japan may also be prohibited without a licence from the country. please call an nec sales representative. fip and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. caution purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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